D16 Taipan

D16 is a portable discrete DAC/amp that showcases iBasso’s excellent digital and analog design expertise. The D16 utilizes an in-house developed FPGA-Master2.0 chip as its core, and employs 16 sets of cascaded 8E PWM-DACs, with a total of 128 PWM-DACs (discrete) for 1bit D/A conversion. The measured THD+N is lower than 0.0001%, which is the best among current portable discrete DACs.

The AMP section is the super class A transistor amplifier that is very similar to the DX320 MAX amplifier, delivering up to 1125mW of clean power to your high end headphones.

Super Class A Discrete Amplifier

The D16 utilizes a similar architecture to the DX320MAX, a super Class A discrete AMP circuit. It incorporates 20 pcs of Low VCEsat (BISS) dual transistors and boasts an impressive output current capability of up to 2A, resulting in a robust output of 1125mW+1125mW@320.

FPGA-Master 2.0

D16’s FPGA-Master2.0 brings together iBasso’s algorithm achievements from the past three years and is the reason they have been able to accomplish breakthroughs for the D16s portable discrete DAC.

The FPGA chip plays the role of signal reorganization and recoding, which generates PWM signals that can be decoded by the subsequent PWM-DAC.

DAC developers are well aware that when the THD reaches a certain level, the presence of noise becomes a hindrance to achieving a greater dynamic range. The D16’s FPGA-Master2.0 boasts an impressive noise shaper that radically lowers the noise floor.

Global clock regeneration technology is employed. Two Accusilicon femtosecond oscillators provide a clock reference for the FPGA. The FPGA regenerates the synchronous low-phase noise clock required by the DSP and USB receiver. 1-bit DACs are very sensitive to clock jitter. iBasso tested a variety of femtosecond oscillators of various brands, and Accusilicon’s audio oscillator has a phase noise as low as -158dBc/Hz [@1kHz]. Compared with the – 145dBc/Hz of a general femtosecond oscillator, the phase noise is reduced by 13dB, which guarantees excellent Jitter control for the D16.

The FPGA in the D16 delivers picosecond-level precise delay control, which can set the 1/0 delay and compensate for the “wiring delay” of the board so that the signals arriving at the DAC end are aligned and strictly synchronized.

With the precise control of FPGA-Master 2.0, 128 independent PWM-DACs operate in FIR mode and combine to form L+, L-, and R+ outputs. Every DAC data bit undergoes careful delay and alignment through rigorous compensation.